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8 - channel differential das with 18 - bit, bipolar, simultaneous sampling adc data sheet AD7609 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assume d by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or pate nt rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features 8 simultaneously sampled inputs true differential inputs true bipolar analog input ranges: 10 v, 5 v single 5 v analog supply and 2.3 v to 5.25 v v drive fully integrated data acquisition solution analog input clamp protection input buffer with 1 m analog input impedance second - order antialiasing analog filter on - chip accurate reference and reference buffer 18- bit adc with 200 ksps on all channels oversampling capability with digital filter flexible parallel/serial interface spi/qspi?/ microwire? /ds p compatible performance 7 kv esd rating on analog input channels 98 db snr, ?107 db thd dynamic range: up to 105 db typical low power: 100 mw standby mode: 25 mw 64- lead lqfp package applications power line monitoring and protection systems multiphase m otor control instrumentation and control systems multi axis positioning systems data acquisition systems (das) companion products external references: adr421 , adr431 digital isolators: adum1402 , adum5000 , adum5402 power: adisim power , supervisor parametric search additional companion products on the AD7609 product page table 1 . high resolution, bipolar in put, simultaneous sampling das solutions resolution single - ended inputs true differential inputs number of simultaneous sampling channels 18 bits ad7608 AD7609 1 8 16 bits ad7606 8 ad7606 -6 6 ad7606 -4 4 14 bits ad7607 8 1 patent p ending . funct ional block diagram v1+ v1? r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb 1m? 1m? clamp clamp t/h v2+ v2? 1m? 1m? clamp clamp t/h v3+ v3? 1m? 1m? clamp clamp t/h v4+ v4? 1m? 1m? clamp clamp t/h v5+ v5? 1m? 1m? clamp clamp t/h v6+ v6? 1m? 1m? clamp clamp t/h v7+ v7? 1m? 1m? clamp clamp t/h v8+ v8? 1m? 1m? clamp clamp t/h 8:1 mux agnd busy frstdata convst a convst b reset range control inputs clk osc refin/refout ref select agnd os 2 os 1 os 0 d out a d out b rd/sclk cs par/ser sel v drive 18-bit sar digital filter parallel/ serial interface 2.5v ref refcapb refcapa serial parallel regcap 2.5v ldo regcap 2.5v ldo av cc av cc db[15:0] AD7609 09760-001 second- order lpf second- order lpf second- order lpf second- order lpf second- order lpf second- order lpf second- order lpf second- order lpf figure 1 .
AD7609 data sheet rev. a | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 companion products ....................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 timing specifications .................................................................. 7 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 15 termino logy .................................................................................... 19 theory of operation ...................................................................... 21 converter details ....................................................................... 21 analog input ............................................................................... 21 adc transfer function ............................................................. 22 internal/external reference ...................................................... 23 typi cal connection diagram ................................................... 24 power - down modes .................................................................. 24 conversion control ................................................................... 25 digital interface .............................................................................. 26 parallel interface ( par /ser sel = 0) ...................................... 26 serial interface ( par /ser s el = 1) ......................................... 26 reading during conversion ..................................................... 27 digital filter ................................................................................ 28 layout guidelines ....................................................................... 32 outline dimensions ....................................................................... 34 ordering guide .......................................................................... 34 revision history 2/12 rev. 0 to rev. a ch anges to analog input ranges section .................................... 21 7/ 11 revision 0: initial version
data sheet AD7609 rev. a | page 3 of 36 general description the AD7609 is an 18 - bit, 8 - channel , true differential, simultaneous sampling analog - to - digital data a cquisition system (das). the part contains analog input clamp protection, a second - order antialias ing filter, a track - and - hold amplifier, an 18- bit charge redistribution successive approximation analog - to - digital converter ( adc ) , a flexible digital filter, a 2.5 v re ference and reference buffer , and high speed serial and parallel interfaces. the AD7609 operates from a single 5 v supply and can accommodate 10 v and 5 v true bipolar differential input signals while samplin g at throughput rates up to 200 ksps for all channels. the input clamp protection circuitry can tolerate voltages up to 16.5 v. t h e AD7609 has 1 m? analog input impedance regardless of sampling frequency. the single supply operation, on - chip filtering , and high input impedance elimi - nate the need for driver op amps and external bipolar supplies. the AD7609 anti alias ing filter has a ? 3 db cutoff frequency of 3 2 khz and provides 40 db anti alias rejection when sampling at 200 ksps . the flexible digital filter is pin driven, yields improvements in snr, and reduces the ? 3 db bandwidth.
AD7609 data sheet rev. a | page 4 of 36 specifications v r ef = 2.5 v external/internal, av cc = 4.75 v to 5.25 v, v drive = 2.3 v to 5.25 v; f sample = 200 ksps, t a = t min to t max , unless otherwise noted. 1 table 2. parameter test conditions/comments min typ max unit dynamic performance f in = 1 khz sine wave unless otherwise noted signal -to - noise ratio (snr) 2 , 3 oversampling by 16; 10 v range; f in = 16 0 hz 98 101 db oversampling by 16; 5 v range; f in = 1 6 0 hz 100 db no oversampling; 10 v range 90 91 db no oversampling; 5 v range 89.5 90.5 db signal -to - (noise + distortion) (sinad) 2 no oversampling; 10 v range 89.5 91 db no oversampling; 5 v range 89 90 db dynamic range no oversampling; 10 v range 91.5 db no oversampling; 5 v range 90.5 db total harmonic distortion (thd) 2 , 3 no oversampling; 10 v range ?107 ? 97 db no oversampling; 5 v range ? 110 ? 96 db peak harmonic or spurious noise (sfdr) 2 ? 108 db intermodulation distortion (imd) 2 fa = 1 khz, fb = 1.1 khz second - order terms ?110 db third - order terms ? 106 db channel -to - channel isolation 2 f in on unselected channels up to 160 khz ? 95 db analog input filter full power bandwidth ?3 db, 10 v range 32 khz ?3 db, 5 v range 23 khz ?0.1 db, 10 v range 13 khz ?0.1 db, 5 v range 10 khz t group delay 10 v range 7.1 s 5 v range 10.2 s dc accuracy resolution no missing codes 18 bits differential nonlinear ity 2 0.75 ?0.99/+2 lsb 4 integral nonlinearity 2 3 7.5 lsb total unadjusted error (tue) 10 v range 10 lsb 5 v range 90 lsb positive full - sca le error 2 , 5 external reference 8 1 40 lsb internal reference 40 lsb positive full - scale error drift external reference 2 ppm/c internal reference 7 ppm/c positive full - scale error matchi ng 2 10 v range 12 80 lsb 5 v range 40 100 lsb bipolar zero code error 2 , 6 10 v range 3 24 lsb 5 v range 3 48 lsb bipolar zero code error d rift 10 v range 10 v/c 5 v range 5 v/c bipolar zero code error matching 2 10 v range 2.7 30 lsb 5 v range 13 65 lsb negative full - scale error 2 , 5 external reference 8 1 40 lsb internal reference 40 lsb negative full - scale error drift external reference 4 ppm/c internal reference 8 ppm/c negative full - scale error matching 2 10 v range 12 80 lsb 5 v range 40 100 lsb
data sheet AD7609 rev. a | page 5 of 36 parameter test conditions/comments min typ max unit analog input differential input voltage ranges vin = vx+ ? (vx?) range = 1; 10 v ?20 +20 v range = 0; 5 v ?10 +10 v absolute voltage input 10 v range, see the analog input clamp protection section ?10 +10 v 5 v range, see the analog input clamp protection section ?5 +5 v common - mode input range ? 4 5 + 4 v cmrr ? 70 db analog input current 10 v, see figure 28 5.4 a 5 v, see figure 28 2.5 a input capacitance 7 5 pf input impedance 1 m reference input/ output reference input voltage range 2.475 2.5 2.525 v dc leakage current 1 a input capacitance 7 ref select = 1 7.5 pf reference output voltage refin/refout 2.49/ 2.505 v reference temper ature coefficient 10 ppm/c logic inputs input high voltage (v inh ) 0.7 v drive v input low voltage (v inl ) 0.3 v drive v input current (i in ) 2 a input capacitance (c in ) 7 5 pf lo gic outputs output high voltage (v oh ) i source = 100 a v drive ? 0.2 v output low voltage (v ol ) i sink = 100 a 0.2 v floating - state leakage current 1 20 a floating - state output capacitance 7 5 pf output coding twos complement conversion rate conversion time all eight channels included 4 s track - and - hold acquisition time 1 s throughput rate per channel, all eight channels included 200 ksps power requirements av cc 4.75 5.25 v v drive 2.3 5.25 v i total digital inputs = 0 v or v drive normal mode (static) 16 22 ma normal mode (operational) 8 f sample = 200 ksps 20 28.5 ma standby mode 5 8 ma shutdow n mode 2 11 a
AD7609 data sheet rev. a | page 6 of 36 parameter test conditions/comments min typ max unit power dissipation normal mode (static) 80 115.5 mw normal mode (operational) 8 f sample = 200 ksps 100 157 mw standby mode 25 42 mw shutdown mode 10 60.5 w 1 temperature range for b version is ?40c to +85c. 2 see the terminology section. 3 this specification applies when reading during a conversion or after a conversion. if reading during a conversion in parallel and serial mode s wi th v drive = 5 v, snr typically reduces by 1.5 db and thd by 3 db . 4 lsb means least significant bit. with 5 v input range, 1 lsb = 76.29 v. with 10 v input range, 1 lsb = 152.58 v. 5 these specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 bipolar zero code error is calculated with respect to the analog input voltage. see the analog input clamp protection section. 7 sample tested during initial release to ensure compliance. 8 operational power/current figure includes contribution when running in oversampling mode.
data sheet AD7609 rev. a | page 7 of 36 timing specification s av cc = 4.75 v to 5.25 v, v drive = 2.3 v to 5.25 v, v ref = 2.5 v external reference/ internal reference, t a = t min to t max , unless otherwise noted. 1 table 3. limit at t min , t max parameter min typ max unit description parallel/serial/byte mode t cycle 1/throughput rate 5 s parallel mode, reading during ; or after conversion v drive = 2.7 v to 5.25 v ; or serial mode: v drive = 3.3 v to 5.25 v, reading during a conversion using d out a and d out b lines 5 s parallel mode reading after conversion v drive = 2.3 v 10.1 s serial mode reading after conversion; v drive = 2.7 v , d out a and d out b lines 11.5 s serial mode reading after a conversion; v drive = 2.3 v, d out a and d out b lines t conv conversion time 3.45 4 4.15 s oversampling off 7.87 9.1 s oversampling by 2 16.05 18.8 s oversampling by 4 33 39 s oversampling by 8 66 78 s oversampling by 16 133 158 s oversampling by 32 257 315 s oversampling by 64 t wake - up standby 100 s stby rising edge t o convst x rising edge; power - up time from standby mode t wake - up shutdown internal reference 30 ms stby rising edge to convst x rising edge; power - up time from shutdown mode external reference 13 ms stby ris ing edge to convst x rising edge; power - up time from shutdown mode t reset 50 ns reset high pulse width t os_setup 20 ns busy to os x pin setup time t os_hold 20 ns busy to os x pin hold time t 1 4 5 ns convst x high to busy high t 2 25 ns mini mum convst x low pulse t 3 25 ns minimum convst x high pulse t 4 0 ns busy falling edge to cs falling edge setup time t 5 2 0.5 ms maximum delay allowed between convst a, convst b rising edges t 6 25 ns maximum time between last cs rising edge and busy falling edge t 7 25 ns minimum delay between reset low to convst x high parallel read operation t 8 0 ns cs to rd setup time t 9 0 ns cs to rd hold time t 10 rd low pulse width 19 ns v drive above 4.75 v 24 ns v drive above 3.3 v 30 ns v drive above 2.7 v 37 ns v drive above 2.3 v t 11 15 ns rd high pulse width t 12 22 ns cs high pulse width (see figure 5 ); cs and rd linked
AD7609 data sheet rev. a | page 8 of 36 limit at t min , t max parameter min typ max unit description t 13 delay from cs until db[15:0] three - state disabled 19 ns v drive above 4.75 v 24 ns v drive above 3.3 v 30 ns v drive above 2.7 v 37 ns v drive above 2.3 v t 14 3 data access time after rd falling edge 19 ns v drive above 4.75 v 24 ns v drive above 3.3 v 30 ns v drive above 2.7 v 37 ns v drive above 2.3 v t 15 6 ns data hold time after rd falling edge t 16 6 ns cs to db[15:0] hold time t 17 22 ns delay from cs rising edge to db[15:0] thr ee - state enabled serial read operation f sclk frequency of serial read clock 20 mhz v drive above 4.75 v 15 mhz v drive above 3.3 v 12.5 mhz v drive above 2.7 v 10 mhz v drive above 2.3 v t 18 delay from cs unti l d out a/d out b three - state disabled/delay from cs until msb valid 18 ns v drive above 4.75 v 2 3 ns v drive above 3.3 v 35 ns v drive = 2.3 v to 2.7 v t 19 3 data access time after sclk rising edge 20 ns v drive above 4.75 v 26 ns v drive above 3.3 v 32 ns v drive above 2.7 v 39 ns v drive above 2.3 v t 20 0.4 t sclk ns sclk low pulse width t 21 0.4 t sclk ns sclk high pulse width t 22 7 sclk rising edge to d out a/d out b valid hold time t 23 22 ns cs rising edge to d out a/d out b three - state enabled frstdata operation t 24 delay from cs falling edge until frstdata three - state disabled 18 ns v drive above 4.75 v 2 3 ns v drive above 3.3 v 30 ns v drive abov e 2.7 v 35 ns v drive above 2.3 v t 25 ns delay from cs falling edge until frstdata high, serial mode 18 ns v drive above 4.75 v 23 ns v drive above 3.3 v 30 ns v drive above 2.7 v 35 ns v drive above 2.3 v t 26 del ay from rd falling edge to frstdata high 19 ns v drive above 4.75 v 23 ns v drive above 3.3 v 30 ns v drive above 2.7 v 35 ns v drive above 2.3 v
data sheet AD7609 rev. a | page 9 of 36 limit at t min , t max parameter min typ max unit description t 27 delay from rd falling edge to frstdata low 22 ns v drive = 3.3 v to 5.25 v 29 ns v drive = 2.3 v to 2.7 v t 28 delay from 18 th sclk falling edge to frstdata low 20 ns v drive = 3.3 v to 5.25 v 27 ns v drive = 2.3 v to 2.7 v t 29 29 ns delay from cs rising edge until frst data three - state enabled 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (30% to 7 0% of v dd ) and timed from a voltage level of 1.6 v. 2 the delay between the convst x signals was measured as the maximum time allowed while ensuring a <40 lsb performance matching between channe l sets. 3 a buffer i s used on the data o utput pins for these measurements, which is equivalent to a load of 20 pf on the output pins. timing diagrams t cycle t 3 t 5 t 2 t 4 t 1 t 7 t reset t conv convst a/ convst b convst a/ convst b busy cs reset 09760-002 figure 2 . convst x timing reading after a conversion t cycle t 3 t 5 t 6 t 2 t 1 t conv convst a/ convst b convst a/ convst b busy cs t 7 t reset reset 09760-003 figure 3 . convst x timing reading during a conversion data: db[15:0] frstdata cs rd in v alid v1 [17:2] v1 [1:0] v2 [17:2] v8 [17:2] v8 [1:0] v2 [1:0] t 10 t 8 t 13 t 24 t 26 t 27 t 14 t 11 t 9 t 16 t 17 t 29 t 15 09760-004 figure 4 . parallel mod e separate cs and rd pulses
AD7609 data sheet rev. a | page 10 of 36 data: db[15:0] frstdata cs, rd v1 [17:2] v1 [1:0] v2 [17:2] v2 [1:0] v7 [17:2] v7 [1:0] v8 [17:2] v8 [1:0] t 12 t 13 t 16 t 17 09760-005 figure 5 . cs and rd linked parallel mode sclk d out a, d out b frstdata cs db17 db14 db13 db1 db0 t 18 t 19 t 21 t 20 t 23 t 29 t 28 t 25 t 22 09760-006 figure 6 . serial read operation
data sheet AD7609 rev. a | page 11 of 36 absolute maximum rat ing s t a = 25c, unless otherwise noted . table 4. parameter rating av cc to agnd ?0.3 v to +7 v v drive to a gnd ?0.3 v to av cc + 0.3 v analog input voltage to agnd 1 16.5 v digital input voltage to a gnd ?0.3 v to v drive + 0.3 v digi tal output voltage to a gnd ?0.3 v to v drive + 0.3 v refin to agnd ?0.3 v to av cc + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range b version ?40c to +85c storage te mperature range ?65c to +150c junction temperature 150c pb/sn temperature, soldering reflow (10 sec to 30 sec) 240(+0)c pb - free temperature, soldering reflow 260(+0)c esd ( all pins except analog inputs) 2 kv esd ( analog input pins only) 7 kv 1 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. these specifications apply to a 4 - layer board. table 5 . thermal resistance package type ja jc unit 64- lead lqfp 45 11 c/w esd caution
AD7609 data sheet rev. a | page 12 of 36 pin configuration an d function descripti ons AD7609 top view (not to scale) 64 63 62 61 60 59 58 57 v1? 56 55 54 53 52 51 50 49 v5+ v4+ v6+ v3+ v2+ v1+ pin 1 v7+ v8+ v2? v3? v4? v5? v6? v7? v8? db13 db12 db11 db14 v drive db1 17 18 19 20 21 22 23 24 25 agnd 26 27 28 29 30 31 32 db2 db3 db4 db5 db6 db7/d out a db9 db10 db8/d out b agnd av cc 1 3 4 frstdata 7 6 5 os 2 2 8 9 10 12 13 14 15 16 11 db0 busy convst b convst a range reset rd/sclk cs par/ser sel os 1 os 0 stby decoupling capacitor pin data output power supply analog input ground pin digital output digital input reference input/output db15 refin/refout 48 46 45 42 43 44 47 41 40 39 37 36 35 34 33 38 agnd av cc refgnd refcapa agnd agnd agnd refcapb refgnd regcap regcap av cc av cc ref select 09760-007 figure 7 . pin configuration table 6 . pin function descriptions pin no. type 1 mnemonic description 1, 37, 38, 48 p av cc analog supply voltage 4.75 v to 5.25 v. this supply voltage is applied to the internal front - end amplifiers and to the adc core. these supply pins should be decoupled to agnd. 2, 26, 35, 40, 41, 47 p agnd analog ground . this pin is the ground reference p oint for all analog circuitry on the AD7609. all analog input signals and external reference signals should be referred to these pins. all six of these agnd pins should connect to the agnd plane of a system. 23 p v drive logic power supply input. the volt age (2.3 v to 5 v) supplied at this pin determines the operating voltage of the interface. this pin is nominally at the same supply as the su pply of the host interface (that is, dsp, fpga). 36, 39 p regcap decoupling capacitor pins for voltage output from internal regulator . these output pins should be decoupled separately to agnd using a 1 f capacitor. the voltage on these output pins is in the range of 2.5 v to 2.7 v. 49, 51, 53, 55, 57, 59, 61, 63 ai + v1 + to v8+ analog input v1+ to analog input v8 + . these pins are the positive terminal of the true differential analog inputs. the analog input range of these channels is determined by the range pin . 50, 52, 54, 56, 58, 60, 62, 64 ai? v1? to v8 ? analog input v1 ? to analog input v 8?. these are the negati ve terminal s of the true differential analog inputs. the analog input range of these channels is determined by the range pin. the signal on this pin should be 180 out of phase with the corresponding vx+ pin. 42 ref refin/ refout reference input/ refere nce output. the on - chip reference of 2.5 v is available on this pin for external use if the ref select pin is set to a logic high. alternatively, the internal reference can be disabled b y setting the ref select pin to a logic low and an external reference of 2.5 v can be applied to this input. see the internal/external reference section. decoupling is required on this pin for both the internal or ex ternal reference options. a 10 f capacitor should be applied from t his pin to ground close to the refgnd pins. 34 di ref select internal/ external reference selection input . logic input. if this pin is set to logic high , the internal reference is selected and is enabled . i f this pin is set to logic low , the internal refer ence is disabled and an external reference voltage must be applied to the refin/refout pin. 44, 45 ref refcapa, refcapb reference buffer output force/sense p ins. these pins must be connected together and decoupled to agnd using a low esr 10 f ceramic cap acitor. 43, 46 ref refgnd reference ground pins . these pins should be connected to agnd.
data sheet AD7609 rev. a | page 13 of 36 pin no. type 1 mnemonic description 8 di range analog input range selection. logic input. the polarity on this pin determines the input range of the analog input channels. if this pin is tied to a logi c high, the analog input range is 10 v for all channels. if this pin is tied to a logic low, the analog input range is 5 v for all channels. a logic change on this pin has an immediate effect on the analog input range. changing this pin during a conversi on is not recommended. see the analog input section for more details. 6 di par / ser sel parallel/ serial interface selection input . logic input. if this pin is tied to a logic low, the parallel in terface is selected. if this pin is tied to a logic high, the serial interface is selected. in s erial mode , the rd /sclk pin functions as the serial clock input. the db7/d out a and db8/d out b pin s function as serial data output s . when the s erial interface is selected , the db[15:9] and db[6:0] pins should be tied to a gnd. 9, 10 d i convst a , convst b conversion start input a, conversion start input b. logic inputs. these logic inputs are used to initiate conversions on the analog input channe ls. for simultaneous sampling of all input channels , convst a and convst b can be shorted together and a single conver sion start signal applied. alternatively, convst a can be used to init iate simultaneous sampling for v1, v2, v3 , and v4 , and convst b can be used to initiate simultaneous samp ling on the other analog inputs (v5, v6, v7 , and v8). this is only possible when oversampling is not switched on. wh en the convst a or convst b pin transiti ons from low to high, the front - end track - and - hold circuitry f or their respective analog inputs is set to hold. this function allows a phase delay to be created inherently between the sets of analog inputs. 13 di cs chip select. this active low logic input frames the data transfer. when both cs and rd are logic low in parallel mode, the output bus ( db[15:0] ) is enabled and the conversion result is output on the parallel data bus lines. in serial mode, the cs is used to frame the serial read tran sfer and clock s out the msb of the serial output data. 12 d i rd /sclk parallel data read control input when parallel interface is selected ( rd )/ serial clock input when serial interface is selected (sclk) . when both cs and rd are logic low in parallel mode, the output bus is enabled. in parallel mode, two rd pulses are required to read the full 18 bits of conversion results from each channel. the first rd pulse outputs db[17:2], and the second rd pulses outputs db[1:0]. in serial mode , this pin acts as the serial clock input for data transfers. the cs falling edge takes the data output lines , d out a and d out b , out of t hree - state and clocks out the msb of the conversion result. the rising edge of sclk clocks all subsequent data bits onto the serial data outputs , d out a and d out b. for further information , see the conversion control section . 14 do busy busy output. this pin transitions to a logic high after both convst a and convst b rising edges and indicates that the conversion process has started. the busy output remains high until the conversion process for all channels is comp lete. the falling edge of busy signals that the conversion data is being latched into the output data registers and will be available to be read after a time , t 4 . any data read while busy is high should be complete before the falling edge of busy occurs. r ising edges on convst a or convst b ha ve no effect whil e the busy signal is high. 11 di reset reset input . when set to logic high, the rising edge of reset resets the AD7609. the part must receive a reset pulse after power - up. t o achieve the specified per formance after the reset signal , the t wake_up shutdown t ime should elapse between power - on and the reset pulse. the reset high pulse should be typically 100 ns wide. if a reset pulse is applied during a conversion , the conversion is aborted. if a reset pul se is applied during a read , the contents of the output registers reset to all zeros. 15 do frstdata digital output . the frstdata output signal indicates when the first channel, v1, is being read back on either the parallel or serial interface. when the cs input is high , the frstdata output pin is in three - state. the falling edge of cs takes frstdata out of three - state. in parallel mode , the falling edge of rd corresponding to the result of v1 then set s the frstdata pin high , indicating that the result from v1 is available on the output data bus. the frstdata output returns to a logic low following the third falling edge of rd . in serial mode , frstdata go es high on the falling edge of cs as this clocks out the msb of v1 on douta. it returns low on the 18th sclk falling edge after the cs falling edge. see the conversion control section for more details. 7 di stby standby mode input. this pin is used to place the AD7609 into one of two power - down modes : standby mode or s hutdown mode. the power - down mode entered depends on the state of the range pin , a s shown in table 8 . when in s tandby mode , all circuitry except the on - chip reference, regulators , and regulator bu ffers is powered down. when in s hutdown mode , all circuitry is powered down.
AD7609 data sheet rev. a | page 14 of 36 pin no. type 1 mnemonic description 5, 4, 3 di os [2:0] o ver sampling mode pins . logic inputs. these inp uts are used to select the over sampling ratio. os 2 is the ms b control bit, and os 0 is the lsb control bit. see the digital filter section for additional details on th e over sampling mode of operation and table 9 for over sampling bit decoding. 33 do/di db15 parallel output data bits , data bit 15. when par /ser sel = 0, this pin act s as three - state parallel digi tal output pin . this pin is used to output db 17 of the conversion result during the first rd pulse and db1 of the same conversion result during the second rd pulse. when par /ser sel = 1, this pin should be tied to a gnd. 32 d o/di db14 parallel output data b its, data bit 14. when par /ser sel = 0, this pin act s as three - state parallel digital output pin. when cs and rd are low , this pin is used to outpu t db 16 of the conversion result during the first rd pulse and db0 of the same conversion result during the second rd pulse. when par /ser sel = 1, this pin should be tied to a gnd. 31 to 27 do db[13:9] p arallel output data bits , data bit 13 to data bit 9. when par /ser sel = 0, these pins act as three - state parallel digital input/output pins. when cs and rd are low, these pins are used to output db15 to db11 of the conversion result during the first rd pulse and output 0 during the second rd pulse. when par /ser sel = 1, these pins should be tied to agnd. 24 do db7/d out a parallel output data bit 7 (db 7)/ serial interface data output pin ( d out a ) . when par /ser sel = 0, this pins acts as a three - state parallel digital input/output pin. when cs and rd are low, this pin is used to output db9 of the conver sion result. when par /ser sel = 1, this pin functions as d out a and outputs serial conversion data. see the conversion control section for further details. 25 do db8 /d out b parallel output data bit 8 (db8)/s erial interface data output pin ( d out b ) . when par /ser sel = 0, this pins acts as a three - state parallel digital input/output pin. when cs and rd are low, this pin is used to output db10 of the conversion result. when par /ser sel = 1, this pin functions as d out b and outputs serial conversion data. see the conversion control section for further details. 22 to 16 d o db[6: 0] parallel outp ut data bits, data bit 6 to data bit 0. when par /ser sel = 0, these pins act as three - state parallel digital input/output pins. when cs and rd are low, these pins are used to output db8 to db2 of the co nversion result during the first rd pulse and output 0 during the second rd pulse. when par /ser sel = 1, these pins should be tied to agnd. 1 refers to classification of pin type; p denotes power, ai denotes analog input, ref denotes reference, di denotes digit al input, do denotes digital output.
data sheet AD7609 rev. a | page 15 of 36 typical performance characteristics ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20k 40k 60k 80k 100k snr (db) input frequenc y (hz) a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e 10 v r a n g e f s a m p l e = 200 k sps f i n = 1 k h z 16384 p o i n t ff t s n r = 91 . 52 d b t h d = ?1 1 1.05 d b 09760-008 figure 8 . fft plot, 10 v range ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20k 40k 60k 80k 100k amplitude (db) input frequenc y (hz) a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e 5 v r a n g e f s a m p l e = 200 k sps f i n = 1 k h z 16,384 p o i n t ff t s n r = 91.12 d b t h d = ?109.77 d b 09760-009 figure 9 . fft plot , 5 v range ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 1 2 3 4 5 6 amplitude (db) input frequenc y (khz) 09760-109 a v cc , v d r i v e = 5 v i n t e r n a l r e f e r e n c e 10 v r a n g e f s a m p l e = 12.5ksps f in = 1hz 8192 point fft s n r = 100.71 d b t h d : ?11 1.74 d b figure 10 . fft plot, 10 v range ?3 ?2 ?1 0 1 2 3 0 32,768 in l (lsb) code 65,536 98,304 131,072 163,840 196,608 229,376 10 v r a n g e a v c c , v d r i v e = 5 v t a = 2 5c f s a m p l e = 2 00 k sps wc p in l = 1.69 lsb wcn in l = ?1.3 lsb 09760-010 figure 11 . typical inl , 10 v range 0 32,768 code 65,536 98,304 131,072 163,840 196,608 229,376 09760-0 1 1 ?1.0 0 1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 dn l (lsb) 10 v r a n g e a v c c , v d r i v e = 5 v t a = 2 5c f s a m p l e = 2 00 k sps wc p dn l = 0.33 lsb wcn dn l = ?0.32 lsb figure 12 . typical dnl , 10 v range ?3 ?2 ?1 0 1 2 3 0 32,768 in l (lsb) code 65,536 98,304 131,072 163,840 196,608 229,376 5 v r a n g e a v c c , v d r i v e = 5 v t a = 2 5c f s a m p l e = 2 00 k sps wc p in l = 1.56 lsb wcn in l = ?1.22 lsb 09760-012 figure 13 . typical inl , 5 v range
AD7609 data sheet rev. a | page 16 of 36 0 32,768 code 65,536 98,304 131,072 163,840 196,608 229,376 09760-013 dnl (lsb) ?1.0 0 1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 5v range av cc , v drive = 5v t a = 25c f sample = 200 ksps wcp inl = 0.45 lsb wcn inl = ?0.38 lsb figure 14. typical dnl, 5 v range 80 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 ?80 nfs error (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 09760-117 figure 15. nfs error vs. temperature 80 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 ?80 pfs error (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 09760-118 figure 16. pfs error vs. temperature 40 ?40 ?25 ?10 5 20 35 50 65 80 ?40 ?32 ?24 ?16 ?8 0 8 16 24 32 nfs/pfs channel matching (lsb) temperature (c) 10v range av cc , v drive = 5v external reference pfs error nfs error 09760-218 figure 17. nfs and pfs error matching 10 8 6 4 2 0 0120k 100k 80k 60k 40k 20k ?2 pfs/nfs error (%fs) source resistance ( ? ) av cc , v drive = 5v f sample = 200 ksps t a = 25c external reference source resistance is matched on the v? input 10v and 5v range 09760-219 figure 18. pfs and nfs error vs. source resistance 80 85 90 95 100 105 10 100 10k 10k 100k snr (dbs) input frequency (hz) no os os 2 os 4 os 8 os 16 os 32 os 64 av cc ,v drive = 5v f sample changes with os rate t a = 25c internal reference 10v range 09760-017 figure 19. snr vs. input frequency, 10 v range
data sheet AD7609 rev. a | page 17 of 36 80 85 90 95 100 105 10 100 10k 10k 100k snr (dbs) input frequenc y (hz) no os os 2 os 4 os 8 os 16 os 32 os 64 a v c c , v drive = 5v f sample changes with os rate t a = 25c internal reference 5v range 09760-018 figure 20 . snr vs. input frequency, 5 v range ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 1 10 100 thd (db) frequenc y (khz) 10 v r a n g e a v c c , v d r i v e = 5 v t a = 2 5c f s a m p l e = 2 00 k sps r source m a tched on v x +, v x ? inputs 10k? 5k? 10? 0? 1.2k? 500? 09760-020 figure 21 . thd vs. input frequency for various source impedances, 10 v range ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 1 10 100 thd (db) frequenc y (khz) 09760-019 5 v r a n g e a v c c , v d r i v e = 5 v t a = 2 5c f s a m p l e = 2 00 k sps r source m a tched on v x +, v x ? inputs 10k? 5k? 10? 0? 1.2k? 500? figure 22 . thd vs. input frequen cy for various source impedances, 5 v range 200 ksps a v cc ,v drive = 5v externa l reference 09760-023 5v range 10v range ?6 ?4 ?2 0 2 4 6 8 ?40 ?20 0 20 40 60 80 bipolar zero error (lsb) temper a ture (c) figure 23 . bipolar zero code error vs. temperature 16 12 8 4 0 ?4 ?8 ?12 ?40 ?25 ?10 5 20 35 50 65 80 ?16 bipolar zero code error matching (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 09760-224 figure 24 . bipolar zero code error matching between channels ?50 ?60 ?70 ?80 ?90 ?100 ?1 10 ?120 ?130 0 160 140 120 100 80 60 40 20 ?140 channel- t o-channe l isol a tion (db) noise frequenc y (khz) a v cc , v drive = 5v interna l reference AD7609 recommended decoupling used f sample = 200ksps t a = 25c 09760-225 5v range 10v range figure 25 . channel - to - channel isolation
AD7609 data sheet rev. a | page 18 of 36 09760-023 80 85 90 95 100 105 1 10 no os os 2 os 4 os 8 os 16 os 32 os 64 dynamic range (db) oversampling r a tio a v cc = v drive = 5v t a = 25c interna l reference f sample scales with os r a tio 10v range 5v range figure 26 . dynamic range vs. oversampling ratio 2.5010 2.5005 2.5000 2.4995 2.4990 2.4985 ?40 ?25 ?10 5 20 35 50 65 80 2.4980 refout voltage (v) temperature (c) av cc = 4.75v av cc = 5v av cc = 5.25v 09760-029 figure 27 . reference output voltage vs. temperature for different supply voltages ?15 ?10 ?5 0 5 10 ?20 ?15 ?10 ?5 0 5 10 15 20 current (a) differentia l analog input vo lt age (vx+ ? (vx?)) (v) +25c v+ +25c v? +85c v? +85c v+ ?40c v? ?40c v+ a v cc , v drive = 5v f sample = 200ksps 09760-025 figure 28 . analog input current vs. input voltage over temperature 22 20 18 16 14 12 10 8 av cc supply current (ma) oversampling ratio av cc , v drive = 5v t a = 25c internal reference f sample varies with os rate no os os 2 os 4 os 8 os 16 os 32 os 64 09760-227 figure 29 . supply current vs. oversampling rate 140 0 1100 1000 900 800 700 600 500 400 300 200 100 60 70 80 90 100 110 120 130 power supply rejection ratio (db) av cc noise frequency (khz) av cc , v drive = 5v internal reference AD7609 recommended decoupling used f sample = 200ksps t a = 25c 10v range 5v range 09760-130 figure 30 . psrr ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 0 ?10 10 100 1k 10k 100k cmrr (db) frequenc y (hz) 10v range 5v range av cc , v drive = 5v t a = 25c f sample = 200ksps internal reference 09760-028 figure 31 . cmrr vs. common - mode ripple frequenc y
data sheet AD7609 rev. a | page 19 of 36 terminology integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a ? lsb below the first code transition , and full scale at ? lsb above the last code transition. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero code error the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, that is, agnd. bipolar zero code error match the difference in bipolar zero code error between any two input channels. positive full - scale error the last transition (from 011 . . . 10 to 011 . . . 11 in twos complement coding ) should o ccur for an analog voltage 1 ? lsb below the nominal full scale (9.999 77 v for the 10 v range and 4.999 88 v for the 5 v range). the positive full - scale error is the deviation of the actual level of the last transition from the ideal level. posit ive full - scale error match the difference in positive full - scale error between any two input channels. negative full - scale error the first transition (from 100 . . . 00 to 100 . . . 01 in twos complement coding) should occur for an analog voltage ? lsb abo ve the negative full scale ( ? 9.9999 23 v for the 10 v range and ? 4.9999 618 for the 5 v range). the negative full - scale error is the deviation of the actual level of the first transition from the ideal level. negative full - scale error match the difference in negative full - scale error between any two input channels. track - and- hold acquisition time the track - and - hold amplifier returns to track mode at the end of the conversion. the track - and - hold acquisition time is the time required for the output of the tra ck - and - hold amplifier to reach its final value, within 1 lsb, after the end of the conversion. see the track - and - hold amplifiers section for more details. signal -to - (noise + distortion) ratio the measured ratio o f signal - to - (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency ( f s /2, excluding dc). the ratio depends on the number of quanti zation levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical signal - to - (noise + distortion) ratio for an ideal n - bit converter with a sine wave input is given by signal - to - ( noise + distortio n ) = (6.02 n + 1.76) db thus, for a n 18- bit converter, this is 110.12 db. total harmonic distortion (thd) the ratio of the rms sum of the harmonics to the fundamental. for the AD7609, it is defined as thd (db) = 20log 1 9 8 7 6 5 4 3 2 v v v v v v v v v 2 2 2 2 2 2 2 2 + + + + + + + where: v 1 is the rms amplitude of the fundamental. v 2 to v 9 are the rms amplitudes of the second through ninth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is determined by a noise peak. intermodulation distortion with inputs consi sting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m , n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n is equal to 0. for example, the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the calculation of the intermodulation distortion is per the thd specification, whe re it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (db).
AD7609 data sheet rev. a | page 20 of 36 power supply rejection (psr) variations in power supply affect the full - scale transition but not the converters linearity. power supply rejection is the maximum change in full - scale transition point due to a change in power supply voltage from the nominal value. the power supply rejection ratio is defined as the ratio of the power in the adc output at f ull - scale f requency , f , to the power of a 200 mv p - p sine wave applied to the adc v dd and v ss supplies of frequency f s . psrr (db) = 10 log ( pf / pf s ) where: pf is equal to the power at frequency f in the adc output. pf s is equal to the power at frequency f s coupled onto the v dd and v ss supplies. channel -to - channel isolation channel - to - channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full - scale, 10 khz sine wave signal to all unselected input ch annels and determining the degree to which the signal attenuates in the selected channel with a 1 khz signal. common - mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc common - mode input at full - scale frequency, f, to the powe r in the output of a full - scale p - p sine wave applied to the common - mode voltage of v in x+ and v in x ? of frequency, f s , cmrr (db) = 2 0 log ( pf / pf s ) where: pf is equal to the power at frequency f in the adc input . pf s is equal to the power at frequency f s in the adc output.
data sheet AD7609 rev. a | page 21 of 36 theory of operation converter details the AD7609 is a data acquisition system that employs a high speed, low power, charge redistribution successive approxima - tion analog - to - digital converter (adc) and allows the simultaneous sampling of eight true differential analog input channels. the a nalog inputs on the AD7609 can accept true bipolar input signals. the range pin is used to select either 10 v or 5 v as the input range. the AD7609 operates from a s ingle 5 v supply. the AD7609 contains input clamp protection, input signal scaling amplifiers, a second - order antialias ing filter, track - and - hold amplifiers, an on - chip reference, reference buffers, a high speed adc , a digital filter , and high speed parallel and serial interfaces. sampling on the AD7609 is controlled using convst x signals. analog input analog input ranges the AD7609 can handle true bipolar input voltages. the logic level on the range pin determines the analog input range of all analog input channels. if this pin is tied to a logic high, the analog input range is 10 v for all channels. if this pin is tied to a logic low, the analog input range is 5 v for all channels. a logic change on this pin ha s an immediate effect on the analog input range ; however , there is a settling time of 80 s typically , in addition to the normal acquisition time requiremen t. the r ecommended practice is to hardwire the range pin according to the desired input range for the system signals. during normal operation, the applied analog input voltage should r emain within the analog input range selected via the range pin. a reset pulse m ust be applied to the part to ensure the analog input channels are configured for the range selected. when in a power - down mode, it is recommended to tie the analog inputs together or both analog input pins (vx+, vx ?) to gnd. as per the analog input clamp protection section, the overvoltage clamp protection is recommended for use in transient overvoltage conditions, and should not remain active for extended periods. stressing the analog inpu ts outside of these conditions may degrade the bipolar zero code error and thd performance of the AD7609. analog input impedance the analog input impedance of the AD7609 is 1 m?. this is a fixed input impedance a nd does not vary with the AD7609 sam - pling frequency. this high analog input impedance eliminates the need for a driver amplifier in front of the AD7609 allowing for di rect connection to the source or sensor. with the need for a driver amplifier eliminated, bipolar supplies can be removed from the signal chain, which are often a source of noise in a system. analog input clamp protection figure 32 shows the analog input structure of the AD7609. each AD7609 analog input contains clamp protection circuitry. despite a single 5 v supply operation , this analog input clamp protection allows f or an input overvoltage up to 16.5 v. 1m? clamp vx+ 1m? clamp vx? second- order lpf r fb r fb 09760-129 figure 32 . analog input circuitry figure 33 shows the current vs . voltage characteristic of the clamp circuit. for input voltages up to 16.5 v , no current flows in the clamp circuit. for input voltages above 16.5 v , the AD7609 clamp circuitry turn s on and clamp s the analog input to 16.5 v. a series resister should be placed on the analog input cha nnels t o limit the current to 10 ma for input voltages above 16.5 v. in an application where there is a series resistance on an analog input channel , vinx+, a corresponding resistance is required on the vinx ? channel ( see figure 34) . if there is no corresponding resister on the vx ? channel , this result s in an offset error on that channel. it is recommended that the input overvoltage clamp protection circuitry be used to protect the AD7609 against transient o vervoltage events. i t is not recom - mended to leave the AD7609 in a condition where the clam p protection circuitry is active ( in normal or pow er - down conditions ) for extended periods because this may degrade the bipolar zero code error performance of the AD7609 . 09760-033 30 ?50 ?40 ?30 ?20 ?10 0 10 20 ?20 ?15 ?10 ?5 0 5 10 15 20 input clamp current (ma) source voltage (v) av cc , v drive = 5v t a = 25c figure 33 . input protection clamp profile 1m? clamp vinx+ 1m? clamp vinx? r fb r fb c r r +10v ?10v AD7609 09760-031 +10v ?10v figur e 34 . input resistance matching on the analog input
AD7609 data sheet rev. a | page 22 of 36 analog input antia liasing filter an analog antialias ing filter is also provided on the AD7609. the filter is a second - order butterworth. figure 35 and figure 36 show the frequency and phase response respectively of the analog antialias ing filter. in the 5 v range , the ? 3 db frequency is typically 2 3 khz. in the 10 v range , the ? 3 db frequency is typically 32 khz. ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 100 1k 10k 100k a ttenu a tion (db) frequenc y (hz) 10 v d i f f 5 v d i f f 09760-032 10v 0.1db tem p 3db ?40c 13,354hz 33,520hz 25c 12,769hz 32,397hz 85c 12,427hz 31,177hz 5v ?40c 10,303hz 24,365hz 25c 9619hz 23,389hz 85c 9326hz 22,607hz figure 35 . analog antia lias ing filter frequency response 09760-133 10 100k 10k 1k phase delay (s) input frequency (hz) 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 5v range 10v range av cc , v drive = 5v f sample = 200ksps t a = 25c figure 36 . analog antia lias ing filter phase res ponse track - and - hold amplifiers the track - and - hold amplifiers on the AD7609 allow the adc to accurately acquire an input sine wave of full - scale amplitude to 18 - bit resolution. the track - and - hold amplifiers samp le their respective inputs simultaneously on the rising edge of convst x. the aperture time for track - and - hold (that is, the delay time between the external convst x signal and the track - and - hold actually going into hold) is well matched, by design, acros s all eight track - and - holds on one device and from device to device. this matching allows more than one AD7609 device to be sampled simultaneously in a system. the end of the conversion process across all eight c hannels is indicated by the falling edge of busy; and it is at this point that the track - and - holds return to track mode and the acquisition time for the next set of conversions begins. the conversion clock for the part is internally generated, and the conv ersion time for all channels is 4 s on the AD7609 . t he busy signal returns low after all eight conversions to indicate the end of the conversion process. on the falling edge of busy, the track - and - hold amplifiers return to track mode. new data can be read from the output register via the parallel, or serial interface after busy goes low; or, alternatively, data from th e previous conversion can be read while busy is high. readin g data from the AD7609 while a conve rsion is in progress has little effect on performance and allows a faster throughput to be achieved. with a v drive > 3.3 v, the snr is reduced by ~1.5 db when reading during a conversion. adc transfer functio n the output coding of the AD7609 is twos complement. the designed code transitions occur midway between successive integer lsb values, that is, 1/2 lsb, 3/2 lsb. the lsb size is fsr/262,144 for the AD7609. the fsr for the AD7609 is 40 v for the 10 v range and 20 v for the 5 v range. the ideal transfer characteristic for the AD7609 is shown in figure 37. 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 ?fs + 1/2lsb 0v ? 1lsb +fs ? 3/2lsb adc code analog input +fsr ? (?fsr) 2 18 lsb = v+ (v?) 5v ref 2.5v 5v code = 131,072 v+ (v?) 10v ref 2.5v 10v code = 131,072 09760-034 figure 37 . AD7609 transfer characteristic the lsb size is dependent on the analog input range selected (see table 7 ). table 7 . output codes and id eal input values description analog input (v+ ? (v ? ) 10 v range analog input v+ ? (v ?) 5 v range digital output code (hex) fsr ? 0.5 lsb +19.999 92 v 9.999961 v 0x 1ffff mids cale + 1 lsb + 152.58 v 76 v 0x 00 001 midscale 0 v 0 v 0x0000 0 midscale C 1 ls b ? 152.58 v ? 76 v 0x 3 ffff ? fsr + 1 lsb ? 19.999 84 v ? 9.99992 v 0x 20 001 ? fsr ? 20 v ? 10 v 0x 20000
data sheet AD7609 rev. a | page 23 of 36 internal/ external reference the AD7609 contains an on - chip 2.5 v band gap reference. the refin/refout pin allo ws access to the 2.5 v reference that generates the on - chip 4.5 v reference internally, or it allows an external reference of 2.5 v to be applied to the AD7609. an externally applied reference of 2.5 v is also amplified to 4.5 v usin g the internal buffer. this 4.5 v buffered reference is the reference used by the sar adc. the ref select pin is a logic input pin that allows the user to select between the in ternal reference and the external reference. if this pin is set to logic high , the internal reference is selected and is enabled ; if this pin is set to logic low , the internal refer - ence is disabled and an external reference voltage must be applied to the refin/refout pin. the internal reference buffer is always enabled. after a reset , the AD7609 operates in the reference mode selected by the ref select pin. decoupling is required on the refin/refout pin for both the internal or external reference options. a 10 f ceramic capacitor is required on the refin/refo ut to ground close to the refgnd pins. the AD7609 contains a reference buffer configured to amplify the ref voltage up to ~4.5 v , as shown in figure 38 . the refcapa and refcapb pins must be shorted together externally and a ceramic capacitor of 10 f applied to refgnd to ensure the reference buffer is in closed - loop operation. the reference voltage available at the refin/refout pin is 2.5 v. when the AD7609 is configured in external reference mode , the r efin/refout pin is a high input impedance pin. for applications using multiple AD7609 devices , the following configurations are recommend ed depending on the application requirements. external reference mode one a dr421 external reference can be used to drive the refin/refout pins of all AD7609 devices ( see figure 39) . in this configuration , each AD7609 refin/refout pin should be decoupled with a 100 nf decoupling capacitor. internal reference mode one AD7609 device, configured to operate in the intern al reference mode, can be used to drive the r emaining AD7609 devices , which are configured to operate in external reference mode ( see figure 40) . the refin/refout pin of the AD7609 , configured in internal reference mode, should be decoupled using a 10 f ceramic decoupling capacitor. the other AD7609 devices, configured in external reference mode, should use a 100 nf decoupling ca pacitor on their refin/refout pins. buf sar 2.5v ref refcapb refin/refout refcapa 10f 09760-035 figure 38 . reference circuitry AD7609 ref select refin/refout + 10f AD7609 ref select refin/refout 100nf AD7609 ref select refin/refout 100nf v drive 09760-036 figure 39 . single external reference driving multiple AD7609 refin /refout pins AD7609 ref select refin/refout AD7609 ref select refin/refout 100nf 0.1f 100nf AD7609 ref select refin/refout 100nf adr421 09760-037 figure 40 . internal reference driving multiple AD7609 refin pins
AD7609 data sheet rev. a | page 24 of 36 typical c onnection d iagram figure 41 shows the typical connection diagram for the ad7 609. there are four av cc supply pins on the part that can be tied together and decoupled using a 100 nf cap acitor at each supply pin and a 10 f capacitor at the supply source. the AD7609 can operate with the in ternal reference or an externally applied reference. in this configuration, the AD7609 is confi g- ured to operate with the internal reference. when using a single AD7609 device on the board , the refin/refout pin should be decoupled with a 10 f capacitor . in an application with multiple AD7609 devices , see the internal/external reference section. the refcapa and refcapb pins are shorted together and decoupled with a 10 f ceramic capacitor . the v drive supply is connected to the same supply as the pro - cessor. the voltage on v drive controls the voltage value of the output logic signals. fo r layout, decoupling , and grounding hints , see the layout guidelines section . after supplies are applied to the AD7609 , a reset should be applied to the AD7609 to ensure that it is configured for the correct mode of operation. p ower - down m odes there are two power - down modes available on the AD7609 . the stby pin contr ols whether the AD7609 is in normal mode or one of the two power - down modes. the two power - down modes available ar e s tandby mode and s hutdown mode. the power - down mode is selected through the state of the range p in when the stby pin is low. table 8 shows the configurations required to choose the desired power - down mode. when the AD7609 is pla ced in s tandby m ode , the current consumption is 8 ma max imum and power - up time is approximately 100 s because the capacitor on the refcapa/refcapb pins must charge up. in s tandby mode , the on - chip reference and regulators remain powered up and the amplifiers and adc core are powered down. when the AD7609 is placed in s hutdown mode , the current consumption is 1 1 a max imum and power up time is about 13 ms. in s hutdown mode , all circuitry is powered down. when the AD7609 is powered up from s hutdown mode, a reset signal must be applied to the AD7609 after the required power - up time has elapsed. table 8. power - down mode select ion power - down mode stby range standby 0 1 shutdown 0 0 av cc agnd v drive + refin/refout db0 to db15 convst a, b cs rd busy reset AD7609 1f 10f 100nf digital supply voltage +2.3v to +5v analog supply voltage 5v 1 eight differential analog input pairs parallel interface 1 decoupling shown on the av cc pin applies to each av cc pin (pin 1, pin 37, pin 38, pin 48). decoupling capacitor can be shared between av cc pin 37 and pin 38. 2 decoupling shown on the regcap pin applies to each regcap pin (pin 36, pin 39). regcap 2 + 10f refcapa refcapb os 2 os 1 os 0 oversampling 100nf v1+ par/ser sel stby ref select range v2+ v3+ v4+ v5+ v6+ v7+ v8+ refgnd v1? v2? v3? v4? v5? v6? v7? v8? v drive v drive microprocessor/ microconverter/ dsp 09760-038 figure 41 . typical connection diagram
data sheet AD7609 rev. a | page 25 of 36 c onversion c ontrol simultaneous sampling on all analog input channels the AD7609 allows simultaneous sampling of all analog input channels. all channels are sampled simultaneously when both convst x pins (convst a, convst b) are tied together. a single convst x signal is used to control both convst x inputs. the rising e dge of this common convst x signal initiates simultaneous sampling on all analog input channels . the AD7609 contains an on - chip oscillator that is used to perform the conversions. the conversion time for all adc channels is t conv . the busy signal indicates to the user when conversions are in progress, so that when the rising edge of convst x is applied, busy goes logic high and transitions low at the end of the entire conversion process. the falling edge of the bu sy signal is used to place all eight track - and - hold amplifiers back into track mode. the falling edge of busy also indicates that the new data can now be read from the parallel bus (db[15:0]) or the serial data lines , d out a and d out b. simultaneously sampl ing two sets of channels the AD7609 also allows the analog input channels to be sampled simultaneously in two sets. this can be used in p ower l ine protection and measurement systems to compensate for phase differ ences between pt and ct transform er s. in a 50 hz system, this allows for up to 9 of phase compensation , and in a 60 hz system, it allows for up to 10 of phase compensation. this is accomplished by pulsing the two convst x pins inde - pendently and is only possible if oversampling is not in use. convst a is used to initiate simultaneous sampling of the first set of channels (v1 to v4) . convst b is used to initiate simultaneous sampling on the seco nd set of analog input channels (v5 to v8) , as illustrated in figure 42 . on the rising edge of convst a, the track - and - hold amplifiers for the first set of channels are placed into hold mode. on the rising edge of convst b, the track - and - hold amplifiers for the second set of channels are placed into hold mode. the conversion process begins after both risin g edges of convst x have occurred; therefore, busy go es high on the rising edge of the later convst x signal. the falling edge of busy also indicates that the new data can n ow be read from the parallel bus or the serial data lines , d out a and d out b. there is no change to the data read process when using two separate convst x signals. connect all unused analog input channel to agnd. the results for any unused channels are still included in the data read because all channels are always converted. 09760-039 convst a convst b busy cs, rd data: db[15:0] frstdata t 5 t conv v1 to v4 track-and-hold enter hold v5 to v8 track-and-hold enter hold AD7609 converts on all 8 channels v1 v8 v2 figure 42 . simultaneous sampling on channel sets using independent convst a/ convst b signals parallel mode
AD7609 data sheet rev. a | page 26 of 36 digital interface the AD7609 provides two interface options: a parallel interface and a high speed serial interface. the required interface mode is selected via the par /ser sel pin. the operation of the interface modes is described in the f ollowing sections. parallel interface ( par /ser sel = 0) data can be read from the AD7609 via the parallel data bus with standard cs and rd signals. to read th e data over the parallel bus, the par /ser sel pin should be tied low. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines , db 15 to db0 , lea ve their high impedance state when both cs and rd are logic low. the rising edge of the cs input signal three - states the bus and the falling edge of the cs input signal takes the bus out of the high impedance state. cs is the control signal that enables the data lines ; it is the function that allows multiple AD7609 devices to share the same parallel data bus. the cs signal can be permanently tied low, and the rd signal can be used to access the conversion results , as shown in figure 4 . a read operation of new data can take place after the busy sign al goes low ( figure 2 ), or , alternatively , a read operation of data from the previous conversion process can take place while busy is high ( figure 3 ). the r d pin is used to read data from the output conversion results register. two rd pulses are required to read the full 18- bit conversion result from each channel. applying a sequence of 16 rd pulses to the AD7609 rd pin clocks the conversion results out from each channel onto the parallel output bus , db[15:0] , in ascending order. the first rd falling edge after busy goes low clocks out db[17:2 ] of the v1 result, the next rd falling edge updates the bus with db[1:0] of the v1 result. it take s 16 rd pulse s to read the eight 18- bit conversion results from the AD7609. the 16 th falling edge of rd clocks out the db[1:0] conversion result for channel v8. when the rd signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (dsp, fpga). when there is only one AD7609 in a system/board and it does not share the parallel bus, data can be read using only one control signal from the digital host. the cs and rd signals can be tied together , as shown in figure 5 . in this case , the data bus comes out of t hree - state on the falling edge of cs / rd . the combined cs and rd signal allows the data to b e clocked out of the AD7609 and to be read by the digital host. in this case , cs is used to frame the data transfer of e ach data channel and 16 cs pulses are required to read the eight channels of data. AD7609 14 busy 12 rd 33:16 db[15:0] 13 cs digital host interrupt 09760-040 figure 43 . AD7609 interface diagram : one AD7609 using the parallel bus ; cs and rd shorted together serial interface ( par /ser sel = 1) to read data back from the AD7609 over the serial interface, the par /ser sel pin should be tied high. the cs and sclk signals are used to transfer data from the AD7609. the AD7609 has two serial data output pins, d out a and d out b. data can be read back from the AD7609 using one or both of these d out lines. for the AD7609 , conversion results from channel v1 to channel v4 first appear on d out a , whereas conversion results from channel v5 to channel v8 first appear on d out b. the cs falling edge takes the data output lines ( d out a and d out b ) out of t hree - state and clocks out the msb of the conver - sion result. the rising edge of sclk clocks all subsequent data bits onto the serial data outputs , d out a and d out b. the cs input can be held low for the entire serial read or it can be pulsed to frame each channel read of 18 sclk cycles. figure 44 shows a read of eight simultaneous conversion results using two d out lines on the AD7609 . in this case, a 72 sclk transfer is used to access data from the AD7609 and cs is held low to frame the entire 72 sclk cycle s. data can also be clocked out using only one d out line, in which case d out a is recom - mended to access all conve rsion data , because the channel data is output in ascending order. for the AD7609 to access all eig ht conversion results on one d out line , a total of 144 sclk cycles are required. these 144 sclk cycles can be framed by one cs signal or each group of 18 sclk cycles can be individually framed by the cs signal. the disad vantage of using only one d out line is that the throughput rate is reduced if reading after conversion. the unused d out line should be left unconnected in serial mode. for the AD7609 , if d out b is to be used as a single d out line , the channel results are o utput in the following order : v5, v6, v7, v8, v1, v2, v3, v4 ; however , the frstdata indicator return s low after v5 is read on d out b.
data sheet AD7609 rev. a | page 27 of 36 figure 6 shows the timing diagram for reading one channel of data, framed by th e cs signal, from the AD7609 in serial mode. the sclk input signal provides the clock source for the serial read o peration. cs goes low to access the data from the ad76 09. the falling edge of cs takes the bus out of three - state and clocks out the msb of the 18 - bit conversion result. this msb is valid on the first falling edge of the sclk after the cs falling edge. the subsequent 17 data bits are clocked out of the AD7609 on the sclk rising edge. data is valid on the sclk falling edge. eighteen clock cycles must be provided to the AD7609 to access each conve rsion result. the frstdata output signal indicates when the first channel, v1, is being read back. when the cs input is high , the frstd ata output pin is in three - state. in serial mode, the falling edge of cs takes frstda ta out of three - state and sets the frstdata pin high indicating that the result from v1 is available on the d out a output data line. the frstdata output returns to a logic low following the 18 th sclk falling edge. if all channels are read on d out b , the frs tdata output does not go high when v1 is being output on this serial data output pin. it only goes high when v1 is available on d out a (and this is when v5 is available on d out b ) . r eading d uring c onversion data can be read from the AD7609 while busy is high and conversions are in progress. this has little effect on the performance of the converter and allows a faster throughput rate to be achieved. a parallel or serial read can be performed during conversions and when oversampling may or may not be in use. figure 3 shows the timing diagram for reading while busy is high in parallel or serial mode. reading during conver - sions allows the full throughput rate to be achieved when using the serial interface with a v drive of 3.3 v to 5.25 v. data can be read from the AD7609 at any time other t han on the falling edge of busy because this is when the output data registers are updat ed wit h the new conversion data. t 6 , outlined in table 3 , should be observed in this condition. v1 v4 v2 v3 v5 v8 v6 v7 sclk d out a d out b cs 72 09760-041 figure 44 . AD7609 serial interface with two d out l ines
AD7609 data sheet rev. a | page 28 of 36 digital filter the AD7609 contains an optional digital filter. this digital filter is a first - order sinc filter. this digital filter should be used in applications where slower throughput rates are used or where higher signal - to - noise ratio or dynamic range is desi rable. the over sampling ratio of the digital filter is controlled using the oversampling pins , os [2:0] ( see table 9 ) . os 2 is the msb control bit and os 0 is the lsb control bit. tabl e 9 provides the oversampling bit decodi ng to select the different over sample rates. the os pins are latched on the falling edge of busy. this set s the over sampli ng rate for the next conversion ( see figure 45) . in addition to t he over sampling function, the output result is decimated to 18 - bit resolution. if the os pins are set to select an os ratio of 8, the next convst x rising edge takes the first sample for each channel and the remaining seven samples for all channels are taken with an internally generated sampling signal. these samples are then averaged to yield an improvement in snr performance. tab le 9 shows typical snr performance for both the 10 v and the 5 v range s . as table 9 indicates, there is an improvement in snr as the os ratio increases. as the os ratio increase s, the 3 db frequency is reduced a nd the allowed sampling frequency is also reduced. in an application where the required sampling frequency is 10 ksps, an os ratio of up to 16 can be used. in this case, the application sees an improvement in snr but the input ? 3 db bandwidth is limited to ~6 khz. the convst a and convst b pins must be tied/driven together when oversampling is turned on. when the over - sampling function is turned on, the busy high time for the conversion process extends. the actual busy high tim e depends on the oversampling rate selected; the higher the oversampling rate, the longer the busy high, or total conversion time, see tabl e 9 . figure 46 shows that the co nversion time extends as the over - sampling rate is increased, and the busy signal lengthens for the different oversampling rates. for example, a sampling frequency of 10 ksps yields a cycle time of 100 s. figure 46 shows os 2 and os 4; for a 10 ksps example, there is adequate cycle time to further increase the oversampling rate and yield greater improve ments in snr performance. in an application where the initial sampling or throughput rate is at 200 ksps, fo r example, and oversampling is turned on, the throughput rate must be reduced to accommodate the longer conversion time and to allow for the read. to achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed du ring the busy high time. the falling edge of busy is used to update the output data registers with the new conver - sion data; therefore, the reading of conversion data should not occur on this edge. figure 47 to figure 53 illustrate the effect of oversampling on the code spread in a dc histogram plot. as the oversample rate is increased, the spread of codes is reduced. (in figure 47 t o figure 53 , av cc = v drive = 5 v and the sampling rate was scaled with os ratio.) convst a, convst b busy os x t os_setup t os_hold conversion n conversion n + 1 oversample rate latched for conversion n + 1 09760-042 figure 45 . os pin timing table 9. oversampling bit decoding (100 hz input signa l) os [2:0] os ratio snr 5 v range (db) snr 10 v range (db) ? 3 db bw 5 v range (khz) ? 3 db bw 10 v range (khz) maximum throughput convst x frequency (khz) 000 no os 90.8 91.5 22 33 200 001 2 93.3 93.9 22 28.9 100 010 4 95.5 96.4 18.5 21.5 50 011 8 98 98.9 11.9 12 25 100 16 100.6 101 6 6 12.5 101 32 101.8 102 3 3 6.25 110 64 102.7 102.9 1.5 1.5 3.125 111 invalid
data sheet AD7609 rev. a | page 29 of 36 cs rd data: db[15:0] busy convst a, convst b t cycle t conv 4s t 4 t 4 t 4 9s 19s os = 0 os = 2 os = 4 09760-043 figure 46 . AD7609 n o oversampling, oversamp l ing 4 , and overs ampling 8 using read after conversion 0 200 400 600 800 1000 1200 1400 1600 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 code 1 2 3 4 5 6 7 8 9 no oversampling number of occurrences 09760-044 2 10 27 83 210 450 727 1062 1384 1373 1 167 840 492 219 100 32 1 1 2 1 figure 47 . histogram of codes no os ( 19 codes ) 0 200 400 600 800 1000 1400 1800 1200 1600 2000 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 code 1 2 3 4 5 6 7 oversampling b y 2 number of occurrences 09760-045 1 12 46 214 599 1 146 1785 1772 1389 788 317 105 15 2 1 figure 48 . histogram of codes os 2 (15 codes ) 500 0 1000 1500 2500 2000 3000 ?5 ?4 ?3 ?2 ?1 0 code 1 2 3 4 oversampling b y 4 number of occurrences 09760-046 5 49 341 1 191 2363 2394 1340 422 79 8 figure 49 . histogram of codes os 4 ( 10 codes ) 0 500 1000 1500 2000 2500 3000 4000 3500 ?4 ?3 ?2 ?1 0 code 1 2 3 oversampling b y 8 number of occurrences 09760-047 1 41 549 229 15 1568 3392 2397 figure 50 . histogram of codes os 8 ( eight codes)
AD7609 data sheet rev. a | page 30 of 36 oversampling b y 16 0 500 1000 1500 2000 3000 4000 2500 3500 4500 ?2 ?3 ?1 0 code 1 2 385 number of occurences 09760-048 3 406 3279 3833 657 14 fig ure 51 . histogram of codes os 16 ( six codes ) 45 5090 341 oversampling b y 32 0 1000 2000 3000 4000 5000 6000 ?2 ?1 code 0 1 number of occurences 09760-049 2716 figure 52 . histogram of codes os 32 ( four codes ) 1 5871 75 oversampling b y 64 0 1000 2000 3000 4000 6000 5000 7000 ?2 ?1 code 0 1 number of occurences 09760-050 2245 figure 53 . histogram of codes C os 64 ( four codes ) w hen the oversampli ng mode is selected , this has the effect of adding a digital filter function after the adc. the different oversampling rates and the convst x sampling frequency produce s different digital filter frequency profiles. figure 54 to figure 59 show the digital filter frequency profiles for the different o versampling rates. the combination of the analog anti alias ing filter and the oversampling digital filter can be used to elimin ate or reduce the complexity of the design of the filter before the AD7609 . the digital filtering combines steep roll - off and linear phase response. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 2 09760-051 figure 54 . digital filter respons e for os 2 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) 09760-052 av cc = 5v v drive = 5v t a = 25c 10v range os by 4 figure 55 . digital filter response for os 4
data sheet AD7609 rev. a | page 31 of 36 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 8 09760-053 figure 56 . digital filter response for os 8 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 16 09760-054 figure 57 . digital filter response for os 16 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 32 09760-055 figure 58 . digital filter response for os 32 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 64 09760-056 figure 59 . digital filter response for os 64
AD7609 data sheet rev. a | page 32 of 36 l ayout g uidelines the printed circuit board that houses the AD7609 should b e designed so that the analog and digital sections are separated and confined to different areas of the board. use a t least one ground plane. it can be common or split between the digital and analog sections. in the case of the split plane, the digital a nd analog ground planes should be joined in only one place, preferably as close as possible to the AD7609. if the AD7609 is in a system where multiple devices require analog - to - digital ground connections, the co nnection should still be made at only one point, a star ground point, which should be established as close as possible to the AD7609 . good connections should be made to the ground plane. avoid sharing one connection for multiple ground pins. individual via s or multiple vias to the ground plane should be used for each ground pin. avoid running digital lines under the devices because doing so couples noise onto the die. allow t he analog ground plane to run under the AD7609 to avoid noise coupling. shield f ast - switching signals like convst a, convst b , or clocks with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. avoid c rossover of digital and analog signals. run t races on layers in close proximity on the board at right angles to each other to reduce the effect of feedthrough through the board. the power supply lines to the av cc and v drive pins on the AD7609 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. where possible , use supply planes . good connec - tions should be made between the AD7609 supply pins and the power tracks on the board; this should involve the use of a single via or multiple vias for each supply pin. good decoupling is also important to lower the supply imped - ance presented to the AD7609 and to reduce the magnitude of the supply spikes. place t he decoupling capacitors close to, ideally right up against, these pins and th eir corresponding ground pins. place t he decoupling capacitors for the refin/ refout pin and th e refcapa and refcapb pins as close as possible to their respective AD7609 pins . where possible , they should be placed on the same side of the board as the AD7609 devic e. figure 60 shows the recommended decoupling on the top layer of the AD7609 board. figure 61 shows bottom layer decoupling. bot tom layer decoupling is for the four av cc pins and the v drive pin. 09760-057 figure 60 . top layer decoupling refin/refout, refcap a, refcapb , and regcap pins 09760-058 figure 61 . bottom layer decoupling
data sheet AD7609 rev. a | page 33 of 36 to ensure good de vice - to - device performance matching in a system that contains multiple AD7609 devices, a symmetrical layout between the AD7609 devices is important. figure 62 shows a layout with two AD7609 devices. the av cc supply plane runs to the right of both devices. the v drive supply tra ck runs to the left of the two AD7609 devices. the reference chip is positioned between both AD7609 devices and the reference voltage track runs north to pin 42 of u1 and south to pin 42 to u2. a solid ground plane is used. the se symmetrical layout principles can be applied to a system that contains more than two AD7609 devices. the AD7609 devices can be placed in a n orth - to - s outh direction w ith the reference voltage located midway between the AD7609 devices and the reference track running in the north - to - south direction similar to figure 62. 09760-059 figure 62 . multiple AD7609 layout , to p layer and supply plane layer
AD7609 data sheet rev. a | page 34 of 36 outline dimensions compliant t o jedec s t andards ms-026-bcd 051706- a t op view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 figure 63 . 64- lead low profile quad flat package [lqfp] (st - 64- 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7609bstz ?40c to +85c 64- lead low profile quad flat package [lqfp] st -64-2 AD7609bstz -rl ?40c to +85c 64- lead low profile quad flat package [lqfp] st -64-2 eval - AD7609edz ?40c to +85c evaluation board for the AD7609 ced1z converter evaluation development 1 z = rohs compliant part.
data sheet AD7609 rev. a | page 35 of 3 6 notes
AD7609 data sheet rev. a | page 36 of 36 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09760 - 0- 2/12(a)

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